A Heuristic Logical Effort Approach for Gate Sizing for CNFET- Based Circuits

Carbon nanotube (CNT) field-effect transistors (CNFETs), as one of the promising candidate emerging technologies, have distinctive device-level characteristics compared to conventional CMOS technology. Logical effort approach, which is an efficient approach for fast delay estimation in CMOS technology, however, is not universally applicable for CNFET-based circuits. In this work, we first identify scenarios where logical effort approach is not applicable. Then we propose a heuristic for delay estimation and gate sizing for such scenarios, as an important integral of the circuit design methodology for CNFET-based circuits. We have conducted two case studies on ripple-carry-adder and address decoder. Results show that logical effort approach can be used when CNFET sizes are large. For small CNFETs, logical effort approach result in up to 12.5% higher delays, where the proposed approach can provide exactly the designs with minimum delays.